Low bit-error-rate communication of data over a communications channel is often considered an important requirement in communications and computation systems. Fulfilling this requirement is increasingly difficult in systems with data rates exceeding multiple gigabits per second (“Gbits/s” or “Gbps”). In the case of an interface or interconnect, either between or within semiconductor chips (also known as dies) that are configured for simultaneous bi-directional communication, there is a problem associated with resource allocation. In a contemporary simultaneous bi-directional communication link, each direction is allocated an equal, fixed bandwidth. In applications such as application specific integrated circuits (ASICs) and memory systems, a required bandwidth in a respective direction on a link is usually unknown a priori and may vary as a function of time. In addition, such a fixed and equal bandwidth allocation may necessitate equal circuit complexity on both sides of the link.
In a simultaneous bi-directional link, the two directions also share a common band of frequencies. This poses an additional challenge of cross-talk between signals on the link.
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